发明名称 DESTRUCTIVE READ ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY
摘要 PROBLEM TO BE SOLVED: To improve access cycle time of a dynamic random access memory (DRAM) system having a plurality of memory cells constituted of rows and columns. SOLUTION: A method comprises a step in which a destructive read mode is enabled, the destruction read mode is a mode for read out destructively a bit of information stored in a DRAM memory cell being addressed. A bit in which information is read destructively is stored temporarily in a temporary storage device. A delay write-back-mode is enabled, this delay write-back-mode is a mode for restoring bit of information in the DRAM memory cell being addressed afterward. Then, execution of the delay write-back-mode is scheduled in accordance with availability of space in the temporary storage device. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007234225(A) 申请公布日期 2007.09.13
申请号 JP20070154901 申请日期 2007.06.12
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 KIRIHATA TOSHIAKI;DHONG SANG HOO;OH HWA-JOON;WORDEMAN MATTHEW
分类号 G11C11/401;G11C11/41;G06F12/08;G11C7/10;G11C11/409 主分类号 G11C11/401
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