发明名称 INTEGRATED CIRCUIT, WAFER, AND MANUFACTURING METHOD FOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit, a wafer and a manufacturing method for the integrated circuit making it difficult to analyze a circuit by reverse engineering or the like, thus precluding the possibility that the content of the circuit is known. SOLUTION: The integrated circuit 11 includes an object circuit 20 and a reverse-engineering prevention circuit 30. The reverse-engineering prevention circuit 30 includes a decrypting circuit 31, a nonvolatile memory 32, and an automatic reading circuit/enable signal generation circuit 33. When a decryption enable signal and decryption data are supplied to the decrypting circuit 31, the decrypting circuit 31 performs authentication using decrypted data; if the authentication is successful, a memory enable signal is output. When supplied with the memory enable signal the nonvolatile memory 32 can write the data, etc. The automatic reading circuit/enable signal generating circuit 33 obtains the data written in the nonvolatile memory 32, generates a circuit enable signal, and supplies the signal to the object circuit 20 to validate the object circuit 20. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007233725(A) 申请公布日期 2007.09.13
申请号 JP20060055092 申请日期 2006.03.01
申请人 FREESCALE SEMICONDUCTOR INC 发明人 OKABE SACHIHIRO;ITO SHUICHI
分类号 G06F21/06 主分类号 G06F21/06
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