Vertical semiconductor arrangement e.g. semiconductor chip stack, for printed circuit board substrate, has auxiliary layer that is bounded on area of relevant main side or includes structure provided with recess, channel, wall and trench

摘要

The arrangement has a wafer (1), and a semiconductor chip (2) including main sides that are arranged opposite to each other and connected with each other. A filling material as underfill (3) is provided in an intermediate space between the wafer and the chip. A structured auxiliary layer (6) is provided on one of the main sides, where the layer is in contact with the underfill. The auxiliary layer is bounded on an area of the relevant main side or includes a structure formed from a group of structures and provided with a recess, channel, wall and a trench. An independent claim is also included for a method for manufacturing a vertical semiconductor arrangement.