SYSTEM FOR INCREASING THE SPEED OF A SUM-OF-ABSOLUTE-DIFFERENCES OPERATION

摘要

An adaptation of the sum-of -absolute- differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first (101) and second (103) operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU) (105), and a destination register (107). An add/subtract enable input on the ALU (105) receives a most significant bit (MSB) of the second set of binary data. The ALU (105) adds the first and second data sets if the MSB is a "0" and subtracts the second data set from the first data set if the MSB is a "1." The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.