| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a method of laying out a semiconductor integrated circuit device capable of improving a yield. <P>SOLUTION: A size of a critical area (Ac(R)) for each functional block is calculated to obtain a size per unit area of Ac(R) for each functional block (ST.2). A danger pattern is extracted for each functional block, the number of extracted danger patterns is calculated, and the number of danger patterns is obtained for each functional block (ST.3). A danger rank is given to respective functional blocks based on the size of Ac(R) per unit area calculated for each functional block and the number of danger patterns (ST.4). The functional blocks are laid from a functional block of a higher danger rank to a block of a lower rank, from the center of a chip to its circumference or a region with higher safety in shot to a region with lower safety in shot (ST.5). <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
