发明名称 |
ARITHMETHIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR |
摘要 |
An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data. |
申请公布号 |
WO2007056675(A3) |
申请公布日期 |
2007.09.13 |
申请号 |
WO2006US60500 |
申请日期 |
2006.11.02 |
申请人 |
QUALCOMM INCORPORATED;AHMED, MUHAMMAD;INGLE, AJAY ANANT;JAMIL, SUJAT |
发明人 |
AHMED, MUHAMMAD;INGLE, AJAY ANANT;JAMIL, SUJAT |
分类号 |
G06F9/355 |
主分类号 |
G06F9/355 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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