AT-SPEED MULTI-PORT MEMORY ARRAY TEST METHOD AND APPARATUS
摘要
A multi-port memory array is tested by simultaneously writing data to the array via two or more write ports, and/or simultaneously reading data from the array via two or more read ports, at the processor operating frequency. Comparing the data read from the array to that written to the array may be performed sequentially or in parallel. Comparator circuits are effectively disabled during normal processor operations. By simultaneously writing and/or reading data via multiple ports, latent electrical marginalities may be exposed. In addition, writing test patterns using multiple write ports and reading the patterns using multiple read ports significantly reduces test time during semiconductor manufacturing tests.
申请公布号
WO2007103745(A2)
申请公布日期
2007.09.13
申请号
WO2007US63097
申请日期
2007.03.01
申请人
QUALCOMM INCORPORATED;KRISHNAMURTHY, ANAND;MUMFORD, CLINT WAYNE;MAMILETI, LAKSHMIKANT;PATEL, SANJAY B.
发明人
KRISHNAMURTHY, ANAND;MUMFORD, CLINT WAYNE;MAMILETI, LAKSHMIKANT;PATEL, SANJAY B.