| 摘要 |
PROBLEM TO BE SOLVED: To provide a cyclic digital/analog conversion circuit capable of reducing a conversion error accompanied by the mismatch of capacitance. SOLUTION: An operation sequence comprising a sampling operation, an electric charge distribution operation, an electric charge storage operation, and an electric charge reset operation is configured so as to express an error transfer function in each bit in a way of a cyclic rational expression. That is, a control circuit 10 controls a voltage application circuit 20 and a connection circuit 30 so that the number of times of the electric charge distribution operations by one capacitor is twice the number of times of the sampling operations or the electric charge storage operations in a series of operations from the sampling of electric charges in each bit to the distribution of the electric charges in the final electric charge distribution operations. Since the error transfer function of each bit is brought into a higher order least value accompanied by the mismatch of capacitance in this way, even if a binary code Din takes any value, an output error accompanied by the mismatch of capacitance can be suppressed to a least value at all times. COPYRIGHT: (C)2007,JPO&INPIT
|
