发明名称 CHIP CARRIER WITH REDUCED INTERFERENCE SIGNAL SENSITIVITY
摘要 Carrier including a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.
申请公布号 US2007210417(A1) 申请公布日期 2007.09.13
申请号 US20060618172 申请日期 2006.12.29
申请人 QIMONDA AG 发明人 BINDER FLORIAN;HANEDER THOMAS;LEHMANN JUDITH;SCHNEEGANS MANFRED;SOMMER GRIT
分类号 H01L29/00 主分类号 H01L29/00
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