Clock generating method for e.g. video integrated circuit, involves determining multiplicity of two counted values, where each value is determined relative to other value around counting mismatch in timely shifted manner

摘要

The method involves providing a clock in relation to a synchronization signal, and controlling the clock by a frequency locked loop (FLL) with respect to phase and/or frequency in relation to the signal. The multiplicity of two counted values is determined, where each counted value is determined by a counting period number of successive periods of the signal. Each counted value is determined relative to the other value around a counting mismatch in a timely shifted manner. An independent claim is also included for a circuit for line connected generation of a clock.