| 摘要 |
A semiconductor memory device and a semiconductor device are provided to prevent the degradation of layout efficiency and performance due to unbalance of scale ratio according to the miniaturization of a control circuit group. A memory array region(401) comprises a memory cell region where memory cells are arranged in a matrix, a plurality of circuits selecting row and column directions of the memory cell region and reading/writing data from/to the selected memory cell, and a data input/output circuit inputting/outputting the read/written data. A control region(402) comprises an address input circuit outputting an address designating the row and column directions selectively according to an address control signal, a control circuit outputting the address control signal according to an external control signal, and a refresh circuit performing a refresh operation by generating the address control signal instead of the external control signal in a standby mode. The control region further comprises a timing generation circuit performing timing adjustment of the address input circuit, the control circuit and the refresh circuit, and a clock generation circuit performing synchronization of the data input/output circuit, the address input circuit, the control circuit, the refresh circuit and the timing generation circuit.
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