CELL ARRAY STRUCTURE OF NAND FLASH MEMORY DEVICE

摘要

A cell array structure of a NAND flash memory is provided to prevent the operating characteristic of memory transistors disposed in an outermost portion of a NAND flash memory from differing from that of memory transistors disposed in the NAND flash memory by disposing a plurality of string/ground select lines at both sides of wordlines wherein the density of an impurity density in a junction region of a memory transistor is substantially the same regardless of the position of the wordline. Active regions are formed in a predetermined region of a semiconductor substrate(110) including an inner region(IR) and an outer region(OR). A memory gate structure is disposed in the inner region, composed of a plurality of wordlines(WL0-WLm) crossing the active region. A select gate structure is disposed at one side and the other side of the memory gate structure, composed of a plurality of string select lines(SSL1,SSL2) crossing the active regions and a plurality of ground select lines(GSL1,GSL2). Impurity regions(170) are formed in the wordlines and the active region between the string select lines and the ground select lines. The string select line and the ground select line that are most adjacent to the memory gate structure are disposed in a boundary between the inner region and the outer region. The active regions at both sides of the wordlines have substantially the same distribution of an impurity density regardless of the position of the wordline.