| 摘要 |
A driver circuit for generating a driving signal by pulse-width modulation (PWM) includes a half-bridge circuit formed essentially of a pair of series-connected FETs. When the level of an ultrasonic signal, or of the driving signal, is to be maximized, the individual FETs are switched at a switching frequency matched to the frequency of the driving signal. When the level of the ultrasonic signal, or the driving signal is to be reduced, on the other hand, the individual FETs are switched with specific timing determined based on the frequency of a clock signal of which period is shorter than that of the driving signal.
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