发明名称 Divisible true dual port memory system supporting simple dual port memory subsystems
摘要 A random access memory circuit and a method for configuring the same. The circuit includes a first array of memory cells including a first plurality of ports and a second plurality of ports, and a second array of memory cells including a third plurality of ports and a fourth plurality of ports. Additionally, the circuit includes a plurality of switches connected to the first plurality of ports and the third plurality of ports respectively or connected to the second plurality of ports and the fourth plurality of ports respectively. Moreover, the circuit includes a plurality of sense amplifiers and a plurality of write drivers.
申请公布号 US7269089(B1) 申请公布日期 2007.09.11
申请号 US20060501616 申请日期 2006.08.08
申请人 发明人
分类号 G11C8/00 主分类号 G11C8/00
代理机构 代理人
主权项
地址