发明名称 |
Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry |
摘要 |
A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the user logic design multiplier in a sum of partial product arrangement in which one of the partial products is generated using the smaller DSP multiplier with the remaining partial products being generated by multipliers implemented using programmable logic circuitry.
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申请公布号 |
US7269617(B1) |
申请公布日期 |
2007.09.11 |
申请号 |
US20030712500 |
申请日期 |
2003.11.12 |
申请人 |
ALTERA CORPORATION |
发明人 |
ESPOSITO BENJAMIN;PELT ROBERT L |
分类号 |
G06F7/523 |
主分类号 |
G06F7/523 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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