Low-voltage CMOS switch with novel clock boosting scheme

摘要

A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from V_DD to (V_DD+KxV_DD). The voltage at the PMOS gate is decreased from V_GND to (V_GND-kxV_GND). The factor k is chosen such that Vout can be sampled through the entire range of Vin=V_GND to V_DD, even where V_DD approaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.