Decode structure with parallel rotation

摘要

A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2ⁿ locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.