| 摘要 |
An AC boundary scan cell is disclosed. For one embodiment the AC boundary scan cell includes a first multiplexer, a second multiplexer, a first data shift register, a second data register, an XOR logic gate, and a third multiplexer. For one such embodiment the AC boundary scan cell includes an SDI line, an SDO line, a TDI line, a TDO line, a ShiftDR signal input line, an AC_Pattern_Clock or ClockDR signal input line, an UpdateDR signal input line, and a Mode signal input line. The AC boundary scan cell also includes an AC_Pattern_Source signal input line and an AC_Test signal input line. For one such embodiment, each line is coupled to receive the corresponding signal from the boundary scan logic.
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