发明名称 |
Multiple patches to on-chip ROM in a processor with a multilevel memory system without affecting performance |
摘要 |
A programmable address decoder is common to the on-chip ROM and on-chip RAM. The programmable address decoder conditionally routes accesses to portions of the ROM to the RAM. The ROM address space is mapped to RAM via a set of configuration registers. This permits patched ROM program code and data table to be stored in on-chip RAM. The patched code and configuration data is stored in an off-chip non-volatile memory. This patch code and the configuration to use is loaded into the RAM and configuration registers on system bootstrap procedure.
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申请公布号 |
US7269707(B2) |
申请公布日期 |
2007.09.11 |
申请号 |
US20040754252 |
申请日期 |
2004.01.09 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MENON AMITABH;GOVINDARAJAN SUBASH CHANDAR;NATARAJAN VENKATESH;SINDAGI VIJAY |
分类号 |
G06F12/08;G06F9/445 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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