| 摘要 |
A host controller transfers data over a bus communication system, under the control of a processor, in individual transactions. A processor interrupt request is generated on completion of a transaction. The host controller comprises logic such that, when a processor interrupt request is generated on completion of a transaction from a first group of the individual transactions, an interrupt request is sent to the processor, whereas when a processor interrupt request is generated on completion of a transaction from a second group of the individual transactions, an interrupt request is not sent to the processor. Further, when a processor interrupt request is generated on completion of a transaction from a third group of the individual transactions, an interrupt request is sent to the processor only when interrupt requests are generated on completion of transactions.
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