发明名称 SHARED MEMORY ARBITER
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a shared memory arbiter capable of obtaining physical layer processing that enables high processing speed and flexibility. <P>SOLUTION: The present invention relates to a physical layer transport composite processing system, used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (303, 307), composite channel processing blocks (305, 309) and a chip-rate processing block (301, 311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a specific wireless mode. The blocks are operated so as to process data in a specific wireless format mode. <P>COPYRIGHT: (C)2007,JPO&INPIT</p>
申请公布号 JP2007228593(A) 申请公布日期 2007.09.06
申请号 JP20070059070 申请日期 2007.03.08
申请人 INTERDIGITAL TECHNOL CORP 发明人 HEPLER EDWARD L;STARSINIC MICHAEL F;BASS DAVID S;DESAI BINISH;LEVI ALAN M;MCCLELLAN GEORGE W;CASTOR DOUGLAS R
分类号 H04B7/26;H04J1/00;H04B1/40;H04B1/707;H04J3/00;H04J4/00;H04L1/00;H04L1/08;H04L12/56;H04W28/18;H04W74/02;H04W80/00;H04W88/02 主分类号 H04B7/26
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