发明名称 |
Complementary Metal Oxide Semiconductor Transistor Technology Using Selective Epitaxy of a Strained Silicon Germanium Layer |
摘要 |
A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.
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申请公布号 |
US2007205468(A1) |
申请公布日期 |
2007.09.06 |
申请号 |
US20070746141 |
申请日期 |
2007.05.09 |
申请人 |
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发明人 |
YEO YEE-CHIA;LIN CHUN-CHIEH;YANG FU-LIANG;HU CHEN MING |
分类号 |
H01L27/092 |
主分类号 |
H01L27/092 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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