发明名称
摘要 A circuit is described comprising a first (10) and a second circuit module (20) and a synchronization module (30). The first and the second module are mutually asynchronous, and are coupled by the synchronization module. The synchronization module (30) comprises: a transfer register (31) for storing data which is communicated between the two circuit modules, a control circuit (32) for controlling the register in response to a respective timing signal (St1, St2) from the first and the second circuit module, the control circuit comprising a control chain for generating a control signal (CR) for the transfer register (31). The control chain includes at least: a repeater (34) for inducing changes in the value of the control signal, at least one edge sensitive element (35) for delaying a change in the signal value until a transition in a selected one of the timing signals is detected.
申请公布号 JP2007525922(A) 申请公布日期 2007.09.06
申请号 JP20070501414 申请日期 2005.02.25
申请人 发明人
分类号 H04L7/00;G06F5/10;H04L7/02 主分类号 H04L7/00
代理机构 代理人
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