发明名称 SEMICONDUCTOR DEVICE, ITS WIRING DESIGN METHOD, AND EVALUATION METHOD
摘要 PROBLEM TO BE SOLVED: To provide a power supply wiring structure in which the mean working precision of vias can be acquired and its wiring design method, and an evaluation method for specifying defective parts resulted from the roughness/fineness of the vias in a short time in a multi-layer wiring technology. SOLUTION: This semiconductor device is provided with a plurality of circuit cell power supply wiring 1 and circuit cell ground wiring 2 arranged so as to be lined up in a first direction on a substrate having a plurality of circuit cells 7; a plurality of base power supply wiring 3 and base ground wiring 4 arranged so as to be lined up in a second direction crossing the first direction, in such a status that wiring widths W1, W2 and W3 are made thinner according as they are made closer to the outer periphery of a circuit cell arrangement region (a), in the upper layer of the circuit cell power supply wiring 1 and the circuit cell ground wiring 2; a plurality of first vias 5 connecting the circuit cell power supply wiring 1 to the base power supply wiring 3 crossing this at the upper part; and a plurality of second vias 6 connecting the circuit cell ground wiring 2 to the base ground wiring 4 crossing this at the upper part. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007227839(A) 申请公布日期 2007.09.06
申请号 JP20060049914 申请日期 2006.02.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OYAMA TOMOKAZU
分类号 H01L21/82;G06F17/50;H01L21/66;H01L21/768;H01L21/822;H01L27/04 主分类号 H01L21/82
代理机构 代理人
主权项
地址