发明名称 Single-Level Parallel-Gated Carry/majority Circuits and Systems Therefrom
摘要 A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.
申请公布号 US2007208797(A1) 申请公布日期 2007.09.06
申请号 US20050593807 申请日期 2005.07.06
申请人 TURNER STEVEN 发明人 TURNER STEVEN
分类号 G06G7/00 主分类号 G06G7/00
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