| 摘要 |
<p>A phase change memory fabricated by a self-align process is provided to minimize parasitic resistance by maximizing an interfacial region of metal and an active material. Transistors are disposed in rows and columns constituting an array. Conductive lines are disposed in columns in the array. Phase change elements(106a,106b,106c,106d) come in contact with the conductive lines, self-aligned with the conductive lines. Lower electrodes come in contact with the phase change elements. Each lower electrode is self-aligned with the conductive layer, coupled to one side of a source-drain path of the transistor. Ground lines(114a,114b) are disposed in the rows in the array. Each ground line in each row is coupled to the other side of the source-drain path of the transistor.</p> |
