发明名称 PARALLEL ARCHITECTURE FOR LOW POWER LINEAR FEEDBACK SHIFT REGISTERS
摘要 The present invention provides an apparatus and method for implementing low-power linear feedback shift registers (LFSR) that efficiently produce single or multiple outputs. In one case of single output generation the gates are permanently connected to the respective flip-flops reducing the number of switches necessary. In the case of multiple outputs the outputs are generated several clock cycles at once, which enables the frequency of operation to be reduced by a factor equal to the number of outputs produced at a time. In either case grouping is utilized for reducing the number of gates necessary and the power dissipation. The invention is applicable to a wide range of applications, including but not limited to data compression, encryption, communication, error correction, built-in self-test, and so forth.
申请公布号 US2007208975(A1) 申请公布日期 2007.09.06
申请号 US20060558721 申请日期 2006.11.10
申请人 NORTH DAKOTA STATE UNIVERSITY 发明人 KATTI RAJENDRA;MAMUN ABDULLAH
分类号 G01R31/28;G06F11/00 主分类号 G01R31/28
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