| 摘要 |
Disclosed is an SSC controller that exercises control to supply a control signal to a phase interpolator which receives an input clock signal and varies the phase of an output clock signal in accordance with the control signal, and to frequency-modulate the output clock signal. In an SSC controller, a counting operation control circuit outputs a counting operation control signal that controls count enable and disable. A p-counter receives a frequency-divided clock signal from a frequency divider and counts the signal when the counting operation control signal from the counting operation control circuit indicates count enable. Upon counting up to a predetermined first value, the counting operation control circuit generates a first output signal and sets its count value to zero. When the counting operation control signal indicates count disable, the p-counter stops counting. An up/down counter receives the first output signal from the p-counter and counts this signal up and down between a predetermined initial value (=0) and a predetermined second value. On the basis of count values from the two counters, a controller outputs the phase control signal to the phase interpolator. The counting operation control circuit, which receives the count values from the two counters and is supplied with a control signal from an SSC control terminal, sets the counting operation control signal to a value indicative of count disable when the supplied control signal indicates count disable and both of the count values from the two counters are at their initial values (=0).
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