| 摘要 |
<p>A phase change memory fabricated by a self-align process is provided to minimize critical lithography processes by performing a self-aligned process and a line lithography process. Transistors(108a,108b,108c,108d) are disposed in rows and columns constituting an array. First conductive lines are disposed in the columns of the array. Second conductive lines are encapsulated by a dielectric material in the rows of the array. Each one of the second conductive lines in each row is coupled to one side of a source-drain path of the transistors. Phase change elements(106a,106b,106c,106d) are positioned between the second conductive lines, coming in contact with the first conductive lines and self-aligned with the first conductive lines. Each phase change element is coupled to the other side of the source-drain path of the transistor. The first conductive lines can be bitlines(112a,112b) and the second conductive lines can be ground lines(114a,114b).</p> |
