| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory control system by which the access error is furthermore reduced by executing a process according to a synchronized state of a clock in a synchronizing memory and a phase adjusted state in a memory controller. SOLUTION: In the memory control system composed of the synchronizing memory and the memory controller for controlling the synchronizing memory, the synchronizing memory includes: an internal synchronizing signal generating circuit for generating an internal clock signal of the synchronizing memory inside, which is synchronized with an external clock signal; a synchronized state decision signal generating circuit for generating the synchronized state decision signal which monitors the synchronized state of the internal clock signal with the external clock signal to show whether the synchronized state of the synchronizing memory inside is in the error state or not; an input node for inputting a phase-adjusted state decision signal from the memory controller; and an error signal output circuit for outputting an error detection signal in accordance with the synchronized state decision signal and the phase-adjusted state decision signal. COPYRIGHT: (C)2007,JPO&INPIT
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