NAND-EEPROM WITH REDUCTION OF FLOATING GATE TO FLOATING GATE COUPLING EFFECT

摘要

For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.