发明名称 |
Method and system for logic equivalence checking |
摘要 |
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.
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申请公布号 |
US7266790(B2) |
申请公布日期 |
2007.09.04 |
申请号 |
US20030656801 |
申请日期 |
2003.09.04 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
PANDEY MANISH;LAI YUNG-TE;SIARKOWSKI BRET;KHOO KEI-YONG;LIN CHIH-CHANG |
分类号 |
G06F17/50;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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