发明名称 Fastplace method for integrated circuit design
摘要 A method for efficient analytical placement of standard cell designs includes obtaining a placement of cells using a wirelength objective function, modifying the placement of cells by cell shifting to redistribute cells to thereby reduce cell overlap, and refining the placement of cells to thereby reduce wirelength using a half-perimeter bounding rectangle-measure. Preferably the wirelength the wirelength objective function is a quadratic objective function which is solved using a hybrid net model. The hybrid net model preferably uses a clique model for two-pin and three-pin nets and a star model for nets having at least four pins. The use of the hybrid net model reduces a number of non-zero entries in a connectivity matrix.
申请公布号 US7266796(B1) 申请公布日期 2007.09.04
申请号 US20050102381 申请日期 2005.04.08
申请人 IOWA STATE UNIVERSITY RESEARCH FOUNDATION, INC. 发明人 CHU CHRIS CHONG-NUEN;VISWANATHAN NATARAJAN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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