发明名称 Signal generating circuit, timing recovery PLL, signal generating system and signal generating method
摘要 A control signal that runs a control oscillator of a signal generation circuit that generates a write clock is taken as a reference signal. That reference signal is supplied to a signal generation circuit that generates a read clock. In the signal generation circuit that generates the read clock, there is no need to generate a reference signal within its own circuits, which makes it possible to supply it to a control oscillator by adding the error timing from reading out the signal against the supplied reference signal. In this way, no means for locking the read clock into the initial frequency is needed and neither is the time for locking the read clock to the initial frequency (lock up time). This makes it possible to reduce the size of the circuit and to reduce the signal read-out time.
申请公布号 US7266170(B2) 申请公布日期 2007.09.04
申请号 US20020114457 申请日期 2002.04.03
申请人 FUJITSU LIMITED 发明人 MATSUNAMI HIROYUKI;OKADA KOUJI
分类号 G11B20/14;H03D3/24;H03L7/06;H03L7/07;H03L7/08;H03L7/089;H03L7/091;H03L7/093;H03L7/099;H03L7/18 主分类号 G11B20/14
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