| 摘要 |
A NAND flash memory device with a burst read latency function is provided to improve performance of a read operation of a memory system including the NAND flash memory device, by reducing cycle time of a read enable signal by removing delay time of an internal clock signal. An interface block(240) receives an external read enable signal and outputs an internal clock signal during a read operation. A buffer clock control circuit(260) operates in response to a data output enable signal and the internal clock signal. A buffer clock generation circuit(280,300) receives the internal clock signal, and generates first and second buffer clock signals according to the control of the buffer clock control signal. A data output buffer(340) outputs read-out data sequentially in response to one of the first and second buffer clock signals. The buffer clock control circuit controls the buffer clock generation circuit in order to generate the second buffer clock signal having a single pulse when the data output enable signal is enabled. The buffer clock control circuit controls the buffer clock generation circuit in order to generate the first buffer clock signal having zero phase difference between with the internal clock signal after the external read enable signal is inputted and the burst read latency time is elapsed. |
