发明名称 Integrated circuit architecture for reducing interconnect parasitics
摘要 An integrated circuit includes a first semiconductor chip including one or more circuits thereon performing substantially core logic functions, the first semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits. The integrated circuit further includes at least a second semiconductor chip including one or more circuits thereon performing substantially input/output interface functions, the second semiconductor chip including multiple signal pads for providing electrical connection to the one or more circuits on the first semiconductor chip. The signal pads on the second semiconductor chip are substantially aligned with and electrically connected to corresponding signal pads on the first semiconductor chip. The first and second semiconductor chips are mutually functionally dependent on one another, such that at least a portion of at least one of the one or more circuits on the first semiconductor chip utilizes at least a portion of at least one of the one or more circuits on the second semiconductor chip, and vice versa. The first and second semiconductor chips are formed using first and second semiconductor fabrication processes, respectively.
申请公布号 US2007194453(A1) 申请公布日期 2007.08.23
申请号 US20060341747 申请日期 2006.01.27
申请人 发明人 CHAKRABORTY KANAD;XU BINGXIONG;ZHOU XINGLING
分类号 H01L23/52;H01L23/48;H01L29/40 主分类号 H01L23/52
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