发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To prevent the malfunction of a logical circuit by reducing a fluctuation in a power source voltage. SOLUTION: The channels 7p and 7n of a p-type transistor Mp and an n-type transistor Mn are formed by tapering in a CMOS inverter shown in a figure. A p-type diffusion layer 5p and an n-type diffusion layer 5n to be connected to a power source and the ground are formed with a larger width. A p-type diffusion layer 6p and an n-type diffusion layer 6n to be connected to output wiring are formed with a smaller width. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007214398(A) 申请公布日期 2007.08.23
申请号 JP20060033250 申请日期 2006.02.10
申请人 NEC CORP 发明人 NAKANO TAKASHI
分类号 H01L21/8238;H01L21/8234;H01L27/06;H01L27/092;H01L29/78 主分类号 H01L21/8238
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