| 摘要 |
A scan read block has a relatively short latch circuit and an acceptable noise margin. The scan read block includes a bit cell array and a scan latch block. The bit cell array includes bit cells transmitting data through a corresponding bit line and inverted bit line. The data is transmitted in response to word line scan signals. The scan latch block includes scan latch circuits latching data stored in a corresponding bit cell through the bit lines and the inverted bit lines. In the scan latch block, the scan latch signal is enabled after the word line scan signals are enabled, and thereafter, data of the bit cell array is latched into a corresponding scan latch circuit during a time when the word line scan signals and the scan latch signal are both enabled.
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