发明名称 MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROBE CARD
摘要 PROBLEM TO BE SOLVED: To perform electric inspection of a semiconductor integrated circuit device having a test pad that has a narrowed pitch. SOLUTION: A semiconductor wafer classified into a plurality of chip regions, where each semiconductor integrated circuit is formed on each of the plurality of chip regions, and a plurality of electrodes connected electrically to each semiconductor integrated circuit are formed, is prepared, and a probe card, having a plurality of contact terminals contactable with the plurality of electrodes, is prepared. In this case, the first sheet 2 including the plurality of contact terminals 7 to be brought into contact with the plurality of electrodes, the second wiring to be connected electrically to the plurality of contact terminals and the first wiring, and shielding metal wiring formed along a signal wire that is easily influenced by the noise among the second wiring, is prepared to a wiring board where the first wiring is formed, and the first sheet is mounted on the wiring board, in a state where the region where the plurality of contact terminals are formed can be pressed against, from the back of the first sheet. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007212471(A) 申请公布日期 2007.08.23
申请号 JP20070084341 申请日期 2007.03.28
申请人 RENESAS TECHNOLOGY CORP 发明人 OKAMOTO MASAYOSHI;MATSUMOTO HIDEYUKI;YORISAKI SHINGO;HASEBE AKIO;MOTOYAMA YASUHIRO;SHIMASE AKIRA
分类号 G01R1/073;G01R31/26;H01L21/66 主分类号 G01R1/073
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