发明名称 Method and system for improving yield of an integrated circuit
摘要 Method and system for improving yield of an integrated circuit are disclosed. The method includes optimizing a design of the integrated circuit according to a set of predefined design parameters to generating design points that meet a set of predefined design specifications, analyzing the design points to form clusters comprising the design points, determining a representative design point from the clusters comprising the design points, running a statistical simulation to determine a yield of the design using the representative design point and a statistical model of manufacturing process variations, generating statistical corners in accordance with results of the statistical simulation, and optimizing the design in accordance with the statistical corners using an iterative process.
申请公布号 US2007198956(A1) 申请公布日期 2007.08.23
申请号 US20060361928 申请日期 2006.02.23
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 LIU HONGZHOU;PHELPS RODNEY M.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址