| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a method for multiple-phase clock generation. <P>SOLUTION: In one embodiment, a multiple-stage voltage controlled oscillator ("VCO") (302) transmits a plurality of clock phases (ck0-ck5) to a clock divider (304) which produces the desired number of clock phase outputs. The clock divider (304) in this embodiment includes a state machine, e.g., a modified Johnson counter (316), that provides a plurality of divided down clock phases, each of which is connected to separate modified shift registers (306-314). Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment, the number of clock phase outputs of the multiple-phase clock is a function which multiplies the number of VCO clock phases by the number of desired states in the modified Johnson counter. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
