| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a structure which prevents occurrence of cracks in metal patterns when a wafer level chip scale package undergoes a thermal cycling test. <P>SOLUTION: A wafer level chip scale package includes a semiconductor chip 410 having multiple edge pads. A lower insulation layer 430 is provided on the semiconductor chip 410 so that the multiple edge pads are exposed. Multiple metal patterns 440 are provided on the lower insulation layer 430 to be electrically connected to the multiple edge pads respectively. An upper insulation layer 450 is provided on the lower insulation layer 430 so that the multiple metal patterns 440 are partially exposed. Multiple solder balls 460, each of which serves as a member for mounting on a printed circuit board, are provided on the exposed portions of the multiple metal patterns. <P>COPYRIGHT: (C)2007,JPO&INPIT |
