| 摘要 |
A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.
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