| 摘要 |
A method for manufacturing a semiconductor device is provided to reduce fabrication costs by forming contact holes of a cell region and a peripheral region at once. A second interlayer dielectric(340) is formed on the entire surface of a semiconductor substrate(300) with a predetermined lower structure. A first mask pattern for exposing contact hole forming regions of a cell region and a peripheral region to the outside is formed on the second interlayer dielectric. A first contact hole(360) for exposing a bit line land plug of the cell region to the outside is formed on the resultant structure by performing an etching process using the first mask pattern as an etch mask. At this time, second and third contact holes(365,370) are formed within the peripheral region in order to expose a hard mask nitride layer of a PMOS(P channel Metal Oxide Semiconductor) and a spacer nitride layer of a junction region to the outside.
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