发明名称 Interconnect structure and method for semiconductor device
摘要 An interconnect method in a semiconductor device may include a step of examining various regions of an inter layer dielectric to identify regions having high densities or concentrations of trench features. A cap insulator layer may be added to the dielectric to assist in outgassing of absorbed impurities from the dielectric, but may be removed from the high density areas to allow the lower density areas to increase outgassing. The lower density areas may then compensate for increased outgassing on the high density areas due to the trench features, and may result in an overall device with a more stable dielectric constant across the device.
申请公布号 US2007197024(A1) 申请公布日期 2007.08.23
申请号 US20060356146 申请日期 2006.02.17
申请人 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 发明人 SHIMOOKA YOSHIAKI;IIJIMA TADASHI
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 代理人
主权项
地址