发明名称 Multilevel QAM symbol timing detecting circuit and multilevel QAM communication signal receiver
摘要 A multilevel symbol timing signal detecting circuit for infallibly detecting the symbol timing of a multilevel QAM signal. When an oversampling I signal is inputted into an I signal histogram creating section (610), the signal is subjected to absolute value operation and a one-symbol length of the I signal is buffered. From the buffered data, the sampling timing corresponding to the oversampling frequency and the amplitude data at the timing are extracted. The amplitude data at each sampling timing is buffered for a predetermined time. From the buffered amplitude data, the histogram of the amplitude data at the sampling timings is created. From the histogram of the ampliture data, the sampling timing corresponding to the amplitude data concerning the highest occurrence frequency so as to acquire the symbol timing.
申请公布号 GB2435383(A) 申请公布日期 2007.08.22
申请号 GB20070011640 申请日期 2005.12.05
申请人 FURUNO ELECTRIC COMPANY, LIMITED 发明人 SHINJI TAMURA
分类号 H04L7/02;H04L27/38 主分类号 H04L7/02
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