发明名称 |
Iterative decoding process |
摘要 |
An apparatus and a communication device including a turbo decoder to decode a block of encoded data bits that includes information bits and error detection code bits. The turbo decoder is able to produce a decoded block which includes decoded information bits and decoded error detection code bits. The Turbo decoder is able to determine from the decoded error detection code bits and calculated error detection code bits possible error patterns of the error detection code bits and is able to generate from the possible error patterns and/or from the error detection code bits reliability metrics.
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申请公布号 |
US7260766(B2) |
申请公布日期 |
2007.08.21 |
申请号 |
US20040986057 |
申请日期 |
2004.11.12 |
申请人 |
INTEL CORPORATION |
发明人 |
LEVY SHARON;YELLIN DANIEL;PERETS YONA |
分类号 |
H03M3/00;H03M13/00;H03M13/03;H03M13/29 |
主分类号 |
H03M3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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