发明名称 Data bus architecture for a semiconductor memory
摘要 A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.
申请公布号 US7260005(B2) 申请公布日期 2007.08.21
申请号 US20050281932 申请日期 2005.11.17
申请人 STMICROELECTRONICS S.R.L. 发明人 CRIPPA LUCA;SANGALLI MIRIAM;MICHELONI RINO
分类号 G11C7/00 主分类号 G11C7/00
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