发明名称 Method of extracting properties of back end of line (BEOL) chip architecture
摘要 A method for analyzing circuit designs includes discretizing a design representation into pixel elements representative of a structure in the design and determining at least one property for each pixel element representing a portion of the design. Then, a response of the design is determined due to local properties across the design.
申请公布号 US7260810(B2) 申请公布日期 2007.08.21
申请号 US20030687475 申请日期 2003.10.16
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 FILIPPI, JR. RONALD G.;FIORENZA GIOVANNI;LIU XIAO HU;MURRAY CONAL EUGENE;NORTHROP GREGORY ALLEN;SHAW THOMAS M.;WACHNIK RICHARD ANDRE';WISNIEWSKI MARY YVONNE LANZEROTTI
分类号 G06F17/50;G03F1/00;G06F19/00 主分类号 G06F17/50
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