发明名称 LEAD FRAME IMPROVING WARPAGE AND SEMICONDUCTOR PACKAGE USING THE SAME
摘要 A lead frame for improving warpage and a semiconductor package using the same are provided to minimize an empty space in a package body by forming a die pad to occupy the package body in 60 to 70 %. A die pad(112) has a chip mounting region on which a semiconductor chip(120) is mounted on a center portion thereof, and a boundary region(112b) positioned around the chip mounting region. Leads(114) are positioned on both sides of the die pad adjacent to the boundary region. Through-holes(113) are formed in the boundary region of the die pad in regular intervals. A width of the boundary region, in which the lead is positioned, is narrow, while a width of the boundary region, in which the lead is not positioned, is wide.
申请公布号 KR20070082410(A) 申请公布日期 2007.08.21
申请号 KR20060015213 申请日期 2006.02.16
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 YOUN, CHEUL JOONG
分类号 H01L23/495 主分类号 H01L23/495
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